Logisches Synthesenetzwerk mit mehreren Dummy-Wahlketten

Réseau de synthèse logique à plusieurs chaînes de sélection factices

Plural dummy select chain logic synthesis network

Abstract

A logic synthesis network for efficiently combining respective bit pairs of first and second operands to produce respective sum bits and a carry bit associated with the most significant sum bit. A dummy generator receives the respective bit pairs and generates first and second dummy sum signals, and first and second pairs of dummy carry signals. A first dummy selector chain selects the appropriate dummy sum and carry signals of all the bits other than the least signifi­cant bit, as a function of the state of the first pair of dummy carry signals generated for the least signifi­cant bit pair. A second dummy select chain selects the appropriate dummy sum and carry signals for all the bit pairs other than the least signficant bit pair, as a function of the state of the second pair of dummy carry signals generated for the least signifi­cant bit pair. Sum generators associated with each bit pair choose between the selected dummy sum signals from the first and second dummy select chains in accordance with the state of the carry-in signal asso­ciated with the least significant bit pair. Carry generators associated with each bit pair choose between the first and second pairs of dummy carry signals at the ends of the first and second dummy select chains, again in accordance with the state of the carry-in signal associated with the least signifi­cant bit pair.

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NO-Patent Citations (1)

    Title
    PATENT ABSTRACTS OF JAPAN vol. 9, no. 308 (P-410)4 December 1985 & JP-A-60 140 424 ( FUJITSU )

Cited By (3)

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    DE-10225862-B4December 17, 2009Ibm Deutschland GmbhÜbertragnetz für eine Übertragauswahladdiereinheit mit ausgewogener Verzögerung zwischen Weiterleitungs- und Generierungspfad
    EP-0849663-A2June 24, 1998Samsung Electronics Co., Ltd.Additionneur à somme conditionnelle utilisant la logique à transisteur de passage
    EP-0849663-A3June 09, 1999Samsung Electronics Co., Ltd.Conditional sum adder using pass-transistor logic