Verfahren und daraus resultierende Vorrichtung zur Kompensation von Prozessparametern in einer CMOS-Treiberschaltung

Method and resulting device for compensating for process variables in a CMOS device driver circuit

Procédé et dispositif obtenu pour compenser les paramètres du processus dans un circuit de commande de type CMOS

Abstract

According to the present invention, an improved CMOS integrated circuit and an improved method of forming the circuit is provided. The circuit has a first FET device (26; 38) and a second FET device (60; 72), and at least one performance characteristic of said first and second FET devices varies in the same manner with the variation of at least one performance related process variable condition. Each of said FET devices has an output signal at least one characteristic of which is changed by a change in the performance related variable condition. The first and second FET devices are connected such that the one output characteristic of the second FET device acts in opposition to the one output characteristic of the first FET device to provide a merged output signal representative of the combined effect of the two FET devices. The second FET device is constructed so as to be more responsive to the variations in said performance related variable condition than the first FET device and to have a weaker output signal than the first FET device, whereby the merged output signal of the two FET devices is maintained relatively constant irrespective of varia­tions in the performance related variable condition.

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Patent Citations (3)

    Publication numberPublication dateAssigneeTitle
    US-4584492-AApril 22, 1986Intel CorporationTemperature and process stable MOS input buffer
    US-4613772-ASeptember 23, 1986Harris CorporationCurrent compensation for logic gates
    US-4845388-AJuly 04, 1989Martin Marietta CorporationTTL-CMOS input buffer

NO-Patent Citations (1)

    Title
    IBM TECHNICAL DISCLOSURE BULLETIN. vol. 28, no. 5, October 1985, NEW YORK US pages 2132 - 2133; 'tolerance compensation for cmos circuits'

Cited By (1)

    Publication numberPublication dateAssigneeTitle
    EP-1006579-A1June 07, 2000CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A.Einrichtung zur Kompensation von Prozess- und Betriebsparametervariation in integrierten Schaltungen CMOS